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precision, very low noise, low input bias current, wide bandwidth jfet operational amplifiers ad8510/ad8512/ad8513 rev. i information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2009 analog devices, inc. all rights reserved. features fast settling time: 500 ns to 0.1% low offset voltage: 400 v maximum low t c v os : 1 v/c typical low input bias current: 25 pa typical at v s = 15 v dual-supply operation: 5 v to 15 v low noise: 8 nv/hz typical at f = 1 khz low distortion: 0.0005% no phase reversal unity gain stable applications instrumentation multipole filters precision current measurement photodiode amplifiers sensors audio pin configurations ad8510 top view (not to scale) null ?in +in v? nc v+ out null 02729-003 nc = no connect 1 2 3 45 6 7 8 ad8510 top view (not to scale) null ?in +in v? nc v+ out null 02729-004 nc = no connect 1 2 3 45 6 7 8 figure 1. 8-lead msop (rm suffix) figure 2. 8-lead soic_n (r suffix) ad8512 out a ?in a +in a v? v+ out b ?in b +in b top view (not to scale) 02729-001 1 2 3 45 6 7 8 ad8512 top view (not to scale) out a ?in a +in a v? v+ out b ?in b +in b 02729-002 1 2 3 45 6 7 8 figure 3. 8-lead msop (rm suffix) figure 4. 8-lead soic_n (r suffix) ad8513 top view (not to scale) out a 1 ?in a 2 +in a 3 v+ 4 +in b 5 out d ?in d +in d v? +in c 14 13 12 11 10 ?in b 6 out b 7 ?in c out c 9 8 02729-005 ad8513 top view (not to scale) out a ?in a +in a v+ +in b out d ?in d +in d v? +in c ?in b out b ?in c out c 0 2729-006 1 2 3 4 5 14 13 12 11 10 6 7 9 8 figure 5. 14-lead soic_n (r suffix) figure 6. 14-lead tssop (ru suffix) general description the ad8510/ad8512/ad8513 are single-, dual-, and quad- precision jfet amplifiers that feature low offset voltage, input bias current, input voltage noise, and input current noise. the combination of low offsets, low noise, and very low input bias currents makes these amplifiers especially suitable for high impedance sensor amplification and precise current measurements using shunts. the combination of dc precision, low noise, and fast settling time results in superior accuracy in medical instruments, electronic measurement, and automated test equipment. unlike many competitive amplifiers, the ad8510/ ad8512/ad8513 maintain their fast settling performance even with substantial capacitive loads. unlike many older jfet amplifiers, the ad8510/ad8512/ad8513 do not suffer from output phase reversal when input voltages exceed the maximum common-mode voltage range. fast slew rate and great stability with capacitive loads make the ad8510/ad8512/ad8513 a perfect fit for high performance filters. low input bias currents, low offset, and low noise result in a wide dynamic range of photodiode amplifier circuits. low noise and distortion, high output current, and excellent speed make the ad8510/ad8512/ad8513 great choices for audio applications. the ad8510/ad8512 are both available in 8-lead narrow soic_n and 8-lead msop packages. msop-packaged parts are only available in tape and reel. the ad8513 is available in 14-lead soic_n and tssop packages. the ad8510/ad8512/ad8513 are specified over the ?40c to +125c extended industrial temperature range.
ad8510/ad8512/ad8513 rev. i | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin configurations ........................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 4 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 typical performance characteristics ............................................. 7 general application information ................................................. 13 input overvoltage protection ................................................... 13 output phase reversal ............................................................... 13 total harmonic distortion (thd) + noise .............................. 13 total noise including source resistors ................................... 13 settling time ............................................................................... 14 overload recovery time .......................................................... 14 capacitive load drive ............................................................... 14 open-loop gain and phase response .................................... 15 precision rectifiers ..................................................................... 16 i-v conversion applications .................................................... 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 20 revision history 2/09rev. h to rev. i changes to figure 25 ...................................................................... 10 changes to ordering guide .......................................................... 20 10/07rev. g to rev. h changes to crosstalk section ........................................................ 18 added figure 58 .............................................................................. 18 6/07rev. f to rev. g changes to figure 1 and figure 2 ................................................... 1 changes to table 1 and table 2 ....................................................... 3 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 6/06rev. e to rev. f changes to figure 23 ........................................................................ 9 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 6/04rev. d to rev. e changes to format ............................................................. universal changes to specifications ................................................................ 3 updated outline dimensions ....................................................... 19 10/03rev. c to rev. d added ad8513 model ....................................................... universal changes to specifications ................................................................ 3 added figure 36 through figure 40 ............................................. 10 added figure 55 and figure 57..................................................... 17 changes to ordering guide .......................................................... 20 9/03rev. b to rev. c changes to ordering guide ............................................................ 4 updated figure 2 ............................................................................ 10 changes to input overvoltage protection section .................... 10 changes to figure 10 and figure 11............................................. 12 changes to photodiode circuits section .................................... 13 changes to figure 13 and figure 14............................................. 13 deleted precision current monitoring section ......................... 14 updated outline dimensions ....................................................... 15 3/03rev. a to rev. b updated figure 5 ............................................................................ 11 updated outline dimensions ....................................................... 15 8/02rev. 0 to rev. a added ad8510 model ....................................................... universal added pin configurations ............................................................... 1 changes to specifications ................................................................. 2 changes to ordering guide ............................................................. 4 changes to tpc 2 and tpc 3 .......................................................... 5 added tpc 10 and tpc 12 .............................................................. 6 replaced tpc 20 ............................................................................... 8 replaced tpc 27 ............................................................................... 9 changes to general application information section .............. 10 changes to figure 5 ........................................................................ 11 changes to i-v conversion applications section ..................... 13 changes to figure 13 and figure 14............................................. 13 changes to figure 17 ...................................................................... 14
ad8510/ad8512/ad8513 rev. i | page 3 of 20 specifications @ v s = 5 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit input characteristics offset voltage (b grade) 1 v os 0.08 0.4 mv ?40c < t a < +125c 0.8 mv offset voltage (a grade) v os 0.1 0.9 mv ?40c < t a < +125c 1.8 mv input bias current i b 21 75 pa ?40c < t a < +85c 0.7 na ?40c < t a < +125c 7.5 na input offset current i os 5 50 pa ?40c < t a < +85c 0.3 na ?40c < t a < +125c 0.5 na input capacitance differential 12.5 pf common mode 11.5 pf input voltage range ?2.0 +2.5 v common-mode rejection ratio cmrr v cm = ?2.0 v to +2.5 v 86 100 db large-signal voltage gain a vo r l = 2 k, v o = ?3 v to +3 v 65 107 v/mv offset voltage drift (b grade) 1 v os /t 0.9 5 v/c offset voltage drift (a grade) v os /t 1.7 12 v/c output characteristics output voltage high v oh r l = 10 k 4.1 4.3 v output voltage low v ol r l = 10 k, ?40c < t a < +125c ?4.9 ?4.7 v output voltage high v oh r l = 2 k 3.9 4.2 v output voltage low v ol r l = 2 k, ?40c < t a < +125c ?4.9 ?4.5 v output voltage high v oh r l = 600 3.7 4.1 v output voltage low v ol r l = 600 , ?40c < t a < +125c ?4.8 ?4.2 v output current i out 40 54 ma power supply power supply rejection ratio psrr v s = 4.5 v to 18 v 86 130 db supply current/amplifier i sy ad8510/ad8512/ad8513 v o = 0 v 2.0 2.3 ma ad8510/ad8512 ?40c < t a < +125c 2.5 ma ad8513 ?40c < t a < +125c 2.75 ma dynamic performance slew rate sr r l = 2 k 20 v/s gain bandwidth product gbp 8 mhz settling time t s to 0.1%, 0 v to 4 v step, g = +1 0.4 s total harmonic distortion (thd) + noise thd + n 1 khz, g = +1, r l = 2 k 0.0005 % phase margin m 44.5 degrees noise performance voltage noise density e n f = 10 hz 34 nv/hz f = 100 hz 12 nv/hz f = 1 khz 8.0 10 nv/hz f = 10 khz 7.6 nv/hz peak-to-peak voltage noise e n p-p 0.1 hz to 10 hz bandwidth 2.4 5.2 v p-p 1 ad8510/ad8512 only.
ad8510/ad8512/ad8513 rev. i | page 4 of 20 electrical characteristics @ v s = 15 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 2. parameter symbol conditions min typ max unit input characteristics offset voltage (b grade) 1 v os 0.08 0.4 mv ?40c < t a < +125c 0.8 mv offset voltage (a grade) v os 0.1 1.0 mv ?40c < t a < +125c 1.8 mv input bias current i b 25 80 pa ?40c < t a < +85c 0.7 na ?40c < t a < +125c 10 na input offset current i os 6 75 pa ?40c < t a < +85c 0.3 na ?40c < t a < +125c 0.5 na input capacitance differential 12.5 pf common mode 11.5 pf input voltage range ?13.5 +13.0 v common-mode rejection ratio cmrr v cm = ?12.5 v to +12.5 v 86 108 db large-signal voltage gain a vo r l = 2 k, v cm = 0 v, v o = ?13.5 v to +13.5 v 115 196 v/mv offset voltage drift (b grade) 1 v os /t 1.0 5 v/c offset voltage drift (a grade) v os /t 1.7 12 v/c output characteristics output voltage high v oh r l = 10 k +14.0 +14.2 v output voltage low v ol r l = 10 k, ?40c < t a < +125c ?14.9 ?14.6 v output voltage high v oh r l = 2 k +13.8 +14.1 v output voltage low v ol r l = 2 k, ?40c < t a < +125c C14.8 ?14.5 v output voltage high v oh r l = 600 +13.5 +13.9 v r l = 600 , ?40c < t a < +125c +11.4 v output voltage low v ol r l = 600 ?14.3 ?13.8 v r l = 600 , ?40c < t a < +125c ?12.1 v output current i out 70 ma power supply power supply rejection ratio psrr v s = 4.5 v to 18 v 86 db supply current/amplifier i sy ad8510/ad8512/ad8513 v o = 0 v 2.2 2.5 ma ad8510/ad8512 ?40c < t a < +125c 2.6 ma ad8513 ?40c < t a < +125c 3.0 ma dynamic performance slew rate sr r l = 2 k 20 v/s gain bandwidth product gbp 8 mhz settling time t s to 0.1%, 0 v to 10 v step, g = +1 0.5 s to 0.01%, 0 v to 10 v step, g = +1 0.9 s total harmonic distortion (thd) + noise thd + n 1 khz, g = +1, r l = 2 k 0.0005 % phase margin m 52 degrees
ad8510/ad8512/ad8513 rev. i | page 5 of 20 parameter symbol conditions min typ max unit noise performance voltage noise density e n f = 10 hz 34 nv/hz f = 100 hz 12 nv/hz f = 1 khz 8.0 10 nv/hz f = 10 khz 7.6 nv/hz peak-to-peak voltage noise e n p-p 0.1 hz to 10 hz bandwidth 2.4 5.2 v p-p 1 ad8510/ad8512 only.
ad8510/ad8512/ad8513 rev. i | page 6 of 20 absolute maximum ratings table 3. parameter rating supply voltage 18 v input voltage v s output short-circuit duration to gnd observe derating curves storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c electrostatic discharge (human body model) 2000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. thermal resistance package type ja 1 jc unit 8-lead msop (rm) 210 45 c/w 8-lead soic_n (r) 158 43 c/w 14-lead soic_n (r) 120 36 c/w 14-lead tssop (ru) 180 35 c/w 1 ja is specified for worst-case conditions, that is, ja is specified for device soldered in circuit board for surface-mount packages. esd caution
ad8510/ad8512/ad8513 rev. i | page 7 of 20 typical performance characteristics input offset voltage (mv) number of amplifiers ?0.5 0 20 40 60 ?0.4 ?0.3 80 100 120 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 v sy = 15v t a = 25c 02729-007 figure 7. input offset voltage distribution t c v os (v/c) number of amplifiers 0 0 5 10 15 1 20 25 30 23456 02729-008 v sy = 15v b grade figure 8. ad8510/ad8512 t c v os distribution t c v os (v/c) number of amplifiers 0 0 5 10 15 1 20 25 30 23 456 02729-009 v sy = 15v a grade figure 9. ad8510/ad8512 t c v os distribution temperature (c) input bias current (pa) ?40 1 10 100 1k ?25 10k 100k ?10 5 20 35 50 65 80 95 110 125 02729-010 v sy = 5v, 15v figure 10. input bias current vs. temperature temperature (c) input offset current (pa) ?40 0.1 1 10 100 ?25 1000 ?10 5 20 35 50 65 80 95 110 125 15v 5v 02729-011 figure 11. input offset current vs. temperature supply voltage (v+ ? v? ) input bias current (pa) 8 0 5 10 15 13 20 25 30 18 23 28 30 35 40 t a = 25c 02729-012 figure 12. input bias current vs. supply voltage
ad8510/ad8512/ad8513 rev. i | page 8 of 20 supply voltage (v+ ? v?) supply current pe r amplifier (ma) 8 1.0 1.1 1.2 13 1.3 1.4 1.6 18 23 28 30 1.7 1.8 1.5 1.9 2.0 t a = 25c 02729-013 figure 13. ad8512 supply current per amplifier vs. supply voltage load current (ma) output voltage (v) 0 0 2 4 10 6 8 12 20 30 40 50 14 16 10 60 70 80 v ol v oh v sy = 15v v sy = 5v v oh v ol 02729-014 figure 14. ad8510/ad8512 output voltage vs. load current temperature (c) supply current per amplifier (ma) ?40 1.00 1.25 1.50 1.75 ?10 2.00 2.25 2.50 520 6580 110 ?25 35 50 95 125 15v 5v 02729-015 figure 15. ad8512 supply current per amplifier vs. temperature supply voltage (v+ ? v?) supply current (ma) 8 1.0 1.2 1.4 13 1.6 1.8 2.2 18 23 28 33 2.4 2.6 2.0 2.8 t a = 25c 02729-016 figure 16. ad8510 supply current vs. supply voltage frequency (hz) gain (db) 10k ?30 ?20 ?10 100k 0 10 30 1m 10m 50m 40 50 20 60 70 ?135 ?90 ?45 0 45 90 135 180 225 270 315 phase (degrees) v sy = 15v r l = 2.5k ? c scope = 20pf m = 52 02729-017 figure 17. open-loop gain and phase vs. frequency temperature (c) supply current (ma) ?40 1.00 1.25 1.50 1.75 ?10 2.00 2.25 2.50 520 6580 110 ?25 35 50 95 125 15v 5v 02729-018 figure 18. ad8510 supply current vs. temperature
ad8510/ad8512/ad8513 rev. i | page 9 of 20 frequency (hz) closed-loop gain (db) 1k ?30 ?20 ?10 10k 0 10 30 1m 10m 50m 40 50 20 60 70 100k 02729-019 v sy = 15v, 5v a v = 100 a v = 1 a v = 10 figure 19. closed-loop gain vs. frequency frequency (hz) cmrr (db) 100 1k 0 40 10k 10m 100m 60 80 20 100 120 100k 1m v sy = 15v 02729-020 figure 20. cmrr vs. frequency frequency (hz) psrr (db) 100 1k 0 40 10k 10m 100m 60 80 20 100 120 100k 1m ?20 ?psrr +psrr v sy = 5v, 15v 02729-021 figure 21. psrr vs. frequency frequency (hz) output impedance ( ? ) 100 1k 0 90 10k 10m 100m 150 180 60 270 300 100k 1m 30 120 210 240 a v = 1 a v = 100 a v = 10 v sy = 15v v in = 50mv 02729-022 figure 22. output im pedance vs. frequency frequency (hz) 1 10 100 1k 1 1k 100 10 10k voltage noise density (nv/ hz) v sy = 5v to 15v 02729-023 figure 23. voltage noise density vs. frequency time (1s/div) voltage (1v/div) v sy = 15v 02729-024 figure 24. 0.1 hz to 10 hz input voltage noise
ad8510/ad8512/ad8513 rev. i | page 10 of 20 frequency (hz) vol t age noise density (nv hz) 0 1 0 105 27 9 175 70 245 280 3 5 35 140 210 46 8 10 v sy = 5v to 15v 02729-025 figure 25. voltage noise density vs. frequency time (1s/div) voltage (5v/div) v sy = 15v r l = 2k ? c l = 100pf a v = 1 02729-026 figure 26. large-signal transient response time (100ns/div) voltage (50mv/div) 02729-027 v sy = 15v r l = 2k ? c l = 100pf a v = 1 figure 27. small-signal transient response load capacitance (pf) small-sign a l overshoot (%) 1 0 10 20 10 30 40 60 100 1k 10k 70 50 80 90 v sy = 15v r l = 2k ? 02729-028 +os ?os figure 28. small-signal overshoot vs. load capacitance frequency (hz) open-loop gain (db) 10k ?10 0 100k 10 20 40 1m 10m 50m 50 30 60 70 ?20 ?30 phase (degrees) ?45 45 90 180 225 135 270 315 ?90 ?135 0 v sy = 5v r l = 2.5k ? c scope = 20pf m = 44.5 02729-029 figure 29. open-loop gain and phase vs. frequency frequency (hz) cmrr (db) 100 40 1k 60 10k 10m 100m 100 80 120 20 0 100k 1m v sy = 5v 02729-030 figure 30. cmrr vs. frequency
ad8510/ad8512/ad8513 rev. i | page 11 of 20 frequency (hz) output impedance ( ? ) 100 60 1k 90 10k 10m 100m 240 120 270 30 0 100k 1m 150 180 210 300 02729-031 v sy = 5v v in = 50mv a v = 100 a v = 10 a v = 1 figure 31. output im pedance vs. frequency time (1s/div) voltage (1v/div) 02729-032 v sy = 5v figure 32. 0.1 hz to 10 hz input voltage noise time (1s/div) voltage (2v/div) v sy = 5v r l = 2k ? c l = 100pf a v = 1 02729-033 figure 33. large-signal transient response time (100ns/div) voltage (50mv/div) v sy = 5v r l = 2k ? c l = 100pf a v = 1 02729-034 figure 34. small-signal transient response load capacitance (pf) small-sign a l overshoot (%) 1 0 10 20 10 30 40 60 100 1k 10k 70 80 50 90 100 v sy = 5v r l = 2k ? 02729-035 ?os +os figure 35. small-signal overshoot vs. load capacitance t c v os (v/c) number of amplifiers 0 1 0 40 25 6 60 80 10 100 90 34 70 50 30 20 v s = 15v 02729-036 figure 36. ad8513 t c v os distribution
ad8510/ad8512/ad8513 rev. i | page 12 of 20 t c v os (v/c) number of amplifiers 0 1 0 40 25 6 60 80 100 34 20 v s = 5v 120 02729-037 figure 37. ad8513 t c v os distribution supply voltage (v+ ? v?) supply current pe r amplifier (ma) 8 13 1.5 1.7 18 33 1.8 1.9 2.0 23 28 1.6 2.1 2.5 2.4 2.3 2.2 t a = 25c 02729-038 figure 38. ad8513 supply current per amplifier vs. supply voltage load current (ma) output voltage (v) 0 10 0 4 20 50 6 8 10 30 40 2 12 16 14 60 70 80 v ol v oh v oh v ol v sy = 15v v sy = 5v 02729-039 figure 39. ad8513 output voltage vs. load current 0 0.5 1.0 1.5 2.0 2.5 3.0 supply current pe r amplifier (ma) temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 02729-040 15v 5v figure 40. ad8513 supply current per amplifier vs. temperature
ad8510/ad8512/ad8513 rev. i | page 13 of 20 general application information input overvoltage protection the ad8510/ad8512/ad8513 have internal protective circuitry that allows voltages as high as 0.7 v beyond the supplies to be applied at the input of either terminal without causing damage. for higher input voltages, a series resistor is necessary to limit the input current. the resistor value can be determined from the formula ma5 ? s s in r vv with a very low offset current of <0.5 na up to 125c, higher resistor values can be used in series with the inputs. a 5 k resistor protects the inputs from voltages as high as 25 v beyond the supplies and adds less than 10 v to the offset. output phase reversal phase reversal is a change of polarity in the transfer function of the amplifier. this can occur when the voltage applied at the input of an amplifier exceeds the maximum common-mode voltage. phase reversal can cause permanent damage to the device and can result in system lockups. the ad8510/ad8512/ad8513 do not exhibit phase reversal when input voltages are beyond the supplies. time (20s/div) 02729-057 voltage (2v/div) v in v out v sy = 5v a v = 1 r l = 10k ? figure 41. no phase reversal total harmonic distortion (thd) + noise the ad8510/ad8512/ad8513 have low thd and excellent gain linearity, making these amplifiers great choices for precision circuits with high closed-loop gain and for audio application circuits. figure 42 shows that the ad8510/ad8512/ad8513 have approximately 0.0005% of total distortion when configured in positive unity gain (the worst case) and driving a 100 k load. frequency (hz) distortion (%) 02729-056 0.01 0.001 0.0001 20 100 1k 10k 20k v sy = 5v r l = 100k ? bw = 22khz figure 42. thd + n vs. frequency total noise including source resistors the low input current noise and input bias current of the ad8510/ad8512/ad8513 make them the ideal amplifiers for circuits with substantial input source resistance. input offset voltage increases by less than 15 nv per 500 of source resistance at room temperature. the total noise density of the circuit is ( ) s s nn ntotal ktr riee 4 2 2 ++= where: e n is the input voltage noise density of the parts. i n is the input current noise density of the parts. r s is the source resistance at the noninverting terminal. k is boltzmanns constant (1.38 10 C23 j/k). t is the ambient temperature in kelvin (t = 273 + c). for r s < 3.9 k, e n dominates and e ntotal e n . the current noise of the ad8510/ad8512/ad8513 is so low that its total density does not become a significant term unless r s is greater than 165 m, an impractical value for most applications. the total equivalent rms noise over a specific bandwidth is expressed as bw ee ntotal ntotal = where bw is the bandwidth in hertz. note that the previous analysis is valid for frequencies larger than 150 hz and assumes flat noise above 10 khz. for lower frequencies, flicker noise (1/f) must be considered.
ad8510/ad8512/ad8513 rev. i | page 14 of 20 settling time settling time is the time it takes the output of the amplifier to reach and remain within a percentage of its final value after a pulse is applied at the input. the ad8510/ad8512/ad8513 settle to within 0.01% in less than 900 ns with a step of 0 v to 10 v in unity gain. this makes each of these parts an excellent choice as a buffer at the output of dacs whose settling time is typically less than 1 s. in addition to the fast settling time and fast slew rate, low offset voltage drift and input offset current maintain the full accuracy of 12-bit converters over the entire operating temperature range. overload recovery time overload recovery, also known as overdrive recovery, is the time it takes the output of an amplifier to recover to its linear region from a saturated condition. this recovery time is par- ticularly important in applications where the amplifier must amplify small signals in the presence of large transient voltages. figure 43 shows the positive overload recovery of the ad8510/ ad8512/ad8513. the output recovers in approximately 200 ns from a saturated condition. 0v ?15v 200mv 0v output input vol t age time (2s/div) v sy = 15v v in = 200mv a v = ?100 r l = 10k ? 02729-053 figure 43. positive overload recovery the negative overdrive recovery time shown in figure 44 is less than 200 ns. in addition to the fast recovery time, the ad8510/ad8512/ ad8513 show excellent symmetry of the positive and negative recovery times. this is an important feature for transient signal rectification because the output signal is kept equally undistorted throughout any given period. time (2s/div) voltage ?200mv 0v 0v +15v 02729-054 input output v sy = 15v a v = ?100 r l = 10k ? figure 44. negative overload recovery capacitive load drive the ad8510/ad8512/ad8513 are unconditionally stable at all gains in inverting and noninverting configurations. each device is capable of driving a capacitive load of up to 1000 pf without oscillation in unity gain using the worst-case configuration. however, as with most amplifiers, driving larger capacitive loads in a unity gain configuration may cause excessive overshoot and ringing, or even oscillation. a simple snubber network significantly reduces the amount of overshoot and ringing. the advantage of this configuration is that the output swing of the amplifier is not reduced, because r s is outside the feedback loop. 7 4 6 ad8510 2 00m v r s c s c l v out v+ v? 02729-055 2 3 figure 45. snubber network configuration
ad8510/ad8512/ad8513 rev. i | page 15 of 20 figure 46 shows a scope plot of the output of the ad8510/ad8512/ ad8513 in response to a 400 mv pulse. the circuit is configured in positive unity gain (worst case) with a load experience of 500 pf. time (1s/div) voltage (200mv/div) v sy = 15v c l = 500pf r l =10k ? 02729-041 figure 46. capacitive load drive without snubber when the snubber circuit is used, the overshoot is reduced from 55% to less than 3% with the same load capacitance. ringing is virtually eliminated, as shown in figure 47 . time (1s/div) vol t age (200mv/div) v sy = 15v r l = 10k ? c l = 500pf r s = 100 ? c s = 1nf 02729-042 figure 47. capacitive load with snubber network optimum values for r s and c s depend on the load capacitance and input stray capacitance and are determined empirically. table 5 shows a few values that can be used as starting points. table 5. optimum values for capacitive loads c load r c 500 pf 100 1 nf 2 nf 70 100 pf 5 nf 60 300 pf open-loop gain and phase response in addition to their impressive low noise, low offset voltage, and offset current, the ad8510/ad8512/ad8513 have excellent loop gain and phase response even when driving large resistive and capacitive loads. compared with competitor a (see figure 49 ) under the same conditions, with a 2.5 k load at the output, the ad8510/ad8512/ ad8513 have more than 8 mhz of bandwidth and a phase margin of more than 52. competitor a, on the other hand, has only 4.5 mhz of band- width and 28 of phase margin under the same test conditions. even with a 1 nf capacitive load in parallel with the 2 k load at the output, the ad8510/ad8512/ad8513 show much better response than competitor a, whose phase margin is degraded to less than 0, indicating oscillation. frequency (hz) gain (db) 10k ?30 ?20 ?10 100k 0 10 30 1m 10m 50m 40 50 20 60 70 ?135 ?90 ?45 0 45 90 135 180 225 270 315 phase (degrees) 02729-043 v sy = 15v r l = 2.5k ? c l = 0pf figure 48. frequency response of the ad8510/ad8512/ad8513 frequency (hz) gain (db) 10k ?30 ?20 ?10 100k 0 10 30 1m 10m 50m 40 50 20 60 70 ?135 ?90 ?45 0 45 90 135 180 225 270 315 phase (degrees) 02729-044 v sy = 15v r l = 2.5k ? c l = 0pf figure 49. frequency response of competitor a
ad8510/ad8512/ad8513 rev. i | page 16 of 20 precision rectifiers time (1ms/div) voltage (1v/div) 02729-046 rectifying circuits are used in a multitude of applications. one of the most popular uses is in the design of regulated power supplies, where a rectifier circuit is used to convert an input sinusoid to a unipolar output voltage. however, there are some potential problems with amplifiers used in this manner. when the input voltage (v in ) is negative, the output is zero, and the magnitude of v in is doubled at the inputs of the op amp. if this voltage exceeds the power supply voltage, it may permanently damage some amplifiers. in addition, the op amp must come out of saturation when v in is negative. this delays the output signal because the amplifier requires time to enter its linear region. although the ad8510/ad8512/ad8513 have a very fast overdrive recovery time, which makes them great choices for the rectification of transient signals, the symmetry of the positive and negative recovery times is also important to keep the output signal undistorted. figure 51. half-wave rectifier signal (out a in figure 50 ) time (1ms/div) voltage (1v/div) 02729-047 figure 50 shows the test circuit of the rectifier. the first stage of the circuit is a half-wave rectifier. when the sine wave applied at the input is positive, the output follows the input response. during the negative cycle of the input, the output tries to swing negative to follow the input, but the power supply restrains it to zero. in a similar fashion, the second stage is a follower during the positive cycle of the sine wave and an inverter during the negative cycle. 8 4 2 1 3 1/2 ad8512 4 8 5 7 6 2/2 ad8512 r2 10k ? r3 10k ? r1 1k ? out a (half wave) out b (full wave) 10v 10v v in 3v p-p 02729-045 figure 52. full-wave rectifier signal (out b in figure 50 ) figure 50. half-wave and full-wave rectifiers
ad8510/ad8512/ad8513 rev. i | page 17 of 20 i-v conversion applications photodiode circuits common applications for i-v conversion include photodiode circuits where the amplifier is used to convert a current emitted by a diode placed at the positive input terminal into an output voltage. the ad8510/ad8512/ad8513s low input bias current, wide bandwidth, and low noise make them each an excellent choice for various photodiode applications, including fax machines, fiber optic controls, motion sensors, and bar code readers. the circuit shown in figure 53 uses a silicon diode with zero bias voltage. this is known as a photovoltaic mode; this configuration limits the overall noise and is suitable for instrumentation applications. 4 7 3 6 2 ad8510 cf r2 rd ct v ee v cc 02729-048 figure 53. equivalent preamplifier photodiode circuit a larger signal bandwidth can be attained at the expense of additional output noise. the total input capacitance (ct) consists of the sum of the diode capacitance (typically 3 pf to 4 pf) and the amplifiers input capacitance (12 pf), which includes external parasitic capacitance. ct creates a pole in the frequency response that can lead to an unstable system. to ensure stability and optimize the bandwidth of the signal, a capacitor is placed in the feedback loop of the circuit shown in figure 53 . it creates a zero and yields a bandwidth whose corner frequency is 1/(2(r2cf)). the value of r2 can be determined by the ratio v / i d where: v is the desired output voltage of the op amp. i d is the diode current. for example, if i d is 100 a and a 10 v output voltage is desired, r2 should be 100 k. rd (see figure 53 ) is a junction resistance that drops typically by a factor of 2 for every 10c increase in temperature. a typical value for rd is 1000 m. because rd >> r2, the circuit behavior is not impacted by the effect of the junction resistance. the maximum signal bandwidth is ctr ft f ma 22 = where ft is the unity gain frequency of the amplifier. cf can be calculated by ftr ct cf 22 = where ft is the unity gain frequency of the op amp, and it achieves a phase margin, m , of approximately 45. a higher phase margin can be obtained by increasing the value of cf. setting cf to twice the previous value yields approximately m = 65 and a maximal flat frequency response, but it reduces the maximum signal bandwidth by 50%. using the previous parameters with a cf 1 pf, the signal bandwidth is approximately 2.6 mhz. signal transmission applications one popular signal transmission method uses pulse-width modulation. high data rates may require a fast comparator rather than an op amp. however, the need for sharp, undistorted signals may favor using a linear amplifier. the ad8510/ad8512/ad8513 make excellent voltage comparators. in addition to a high slew rate, the ad8510/ ad8512/ad8513 have a very fast saturation recovery time. in the absence of feedback, the amplifiers are in open-loop mode (very high gain). in this mode of operation, they spend much of their time in saturation. the circuit shown in figure 54 was used to compare two signals of different frequencies, namely a 100 hz sine wave and a 1 khz triangular wave. figure 55 shows a scope plot of the resulting output waveforms. a pull-up resistor (typically 5 k) can be connected from the output to v cc if the output voltage needs to reach the positive rail. the trade-off is that power consumption is higher. v out v1 v2 4 2 6 7 3 ?15v +15 v 02729-049 figure 54. pulse-width modulator
ad8510/ad8512/ad8513 rev. i | page 18 of 20 time (2ms/div) voltage (5v/div) 02729-050 the ad8510 single has two additional active terminals that are not present on the ad8512 dual or ad8513 quad parts. these pins are labeled null and are used for fine adjustment of the input offset voltage. although the guaranteed maximum offset voltage at room temperature is 400 v and over the ?40c to +125c range is 800 mv maximum, this offset voltage can be reduced by adding a potentiometer to the null pins as shown in figure 58 . with the 20 k potentiometer shown, the adjustment range is approximately 3.5 mv. the potentiometer parallels low value resistors in the drain circuit of the jfet differential input pair and allows unbalancing of the drain currents to change the offset voltage. if offset adjustment is not required, these pins should be left unconnected. caution should be used when adding adjusting potentiometers to any op amp with this capability for several reasons. first, there is gain from these nodes to the output; therefore, capacitive coupling from noisy traces to these nodes will inject noise into the signal path. second, the temperature coefficient of the potentiometer will not match the temperature coefficient of the internal resistors, so the offset voltage drift with temperature will be slightly affected. third, this provision is for adjusting the offset voltage of the op amp, not for adjusting the offset of the overall system. although it is tempting to decrease the value of the potentiometer to attain more range, this will adversely affect the dc and ac parameters. instead, increase the potentiometer to 50 k to decrease the range if needed. figure 55. pulse-width modulation crosstalk crosstalk, also known as channel separation, is a measure of signal feedthrough from one channel to another on the same ic. the ad8512/ad8513 have a channel separation of better than ?90 db for frequencies up to 10 khz and of better than ?50 db for frequencies up to 10 mhz. figure 57 shows the typical channel separation behavior between amplifier a (driving amplifier) and each of the following: amplifier b, amplifier c, and amplifier d. v out 1 2 7 6 5 4 3 8 +v s 20k? 2.2k ? 5k? 5k ? ?v s v in 18v p-p crosstalk = 20 log v out 10v in 02729-052 1 5 4 7 3 6 2 ad8510 input output v+ v os trim range is typically 3.5mv 20k? v? ? + 0 2729-058 figure 56. crosstalk test circuit 02729-051 frequency (hz) channel sepa r a tion (db) 100 ?160 10k ?140 ?120 ?80 1k ?60 ?20 ?40 100k 1m 10m ?100 0 ch d ch c ch b figure 58. optional o ffset nulling circuit figure 57. channel separation
ad8510/ad8512/ad8513 rev. i | page 19 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 59. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 60. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-ab-1 figure 61. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ab 060606-a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 45 figure 62. 14-lead standard small outline package [soic_n] narrow body (r-14) dimensions shown in millimeters and (inches)
ad8510/ad8512/ad8513 rev. i | page 20 of 20 ordering guide model temperature range package desc ription package option branding ad8510armz-reel 1 ?40c to +125c 8-lead msop rm-8 b7a# ad8510armz 1 ?40c to +125c 8-lead msop rm-8 b7a# ad8510ar ?40c to +125c 8-lead soic_n r-8 ad8510arz 1 ?40c to +125c 8-lead soic_n r-8 ad8510arz-reel 1 ?40c to +125c 8-lead soic_n r-8 ad8510arz-reel7 1 ?40c to +125c 8-lead soic_n r-8 ad8510br ?40c to +125c 8-lead soic_n r-8 ad8510br-reel ?40c to +125c 8-lead soic_n r-8 ad8510brz 1 ?40c to +125c 8-lead soic_n r-8 ad8510brz-reel 1 ?40c to +125c 8-lead soic_n r-8 ad8510brz-reel7 1 ?40c to +125c 8-lead soic_n r-8 AD8512ARMZ-reel 1 ?40c to +125c 8-lead msop rm-8 b8a# AD8512ARMZ 1 ?40c to +125c 8-lead msop rm-8 b8a# ad8512ar ?40c to +125c 8-lead soic_n r-8 ad8512ar-reel ?40c to +125c 8-lead soic_n r-8 ad8512ar-reel7 ?40c to +125c 8-lead soic_n r-8 ad8512arz 1 ?40c to +125c 8-lead soic_n r-8 ad8512arz-reel 1 ?40c to +125c 8-lead soic_n r-8 ad8512arz-reel7 1 ?40c to +125c 8-lead soic_n r-8 ad8512br ?40c to +125c 8-lead soic_n r-8 ad8512br-reel ?40c to +125c 8-lead soic_n r-8 ad8512br-reel7 ?40c to +125c 8-lead soic_n r-8 ad8512brz 1 ?40c to +125c 8-lead soic_n r-8 ad8512brz-reel 1 ?40c to +125c 8-lead soic_n r-8 ad8512brz-reel7 1 ?40c to +125c 8-lead soic_n r-8 ad8513ar ?40c to +125c 14-lead soic_n r-14 ad8513ar-reel ?40c to +125c 14-lead soic_n r-14 ad8513ar-reel7 ?40c to +125 c 14-lead soic_n r-14 ad8513arz 1 ?40c to +125c 14-lead soic_n r-14 ad8513arz-reel 1 ?40c to +125c 14-lead soic_n r-14 ad8513arz-reel7 1 ?40c to +125c 14-lead soic_n r-14 ad8513aru ?40c to +125c 14-lead tssop ru-14 ad8513aru-reel ?40c to +125c 14-lead tssop ru-14 ad8513aruz 1 ?40c to +125c 14-lead tssop ru-14 ad8513aruz-reel 1 ?40c to +125c 14-lead tssop ru-14 1 z = rohs compliant part, # denotes rohs co mpliant product may be top or bottom marked. ?2002C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02729-0-2/09(i)

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